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Oklahoma State University

LOW-POWER AND HIGH-PERFORMANCE SRAM DESIGN IN HIGH VARIABILITY ADVANCED CMOS TECHNOLOGY

Date: 
Tuesday, March 21, 2017 - 10:00am to 11:30am
Location: 
Engineering South 201
Dissertation Defense
LOW-POWER AND HIGH-PERFORMANCE SRAM DESIGN IN HIGH VARIABILITY ADVANCED CMOS TECHNOLOGY
 
By: Samira Ataei
 
Advisor:  Professor James E. Stine
 
Abstract: As process technologies shrink, the size and number of memories on a chip are exponentially in- creasing. Embedded SRAMs are a critical component in modern digital systems, and they strongly impact the overall power, performance, and area. To promote memory-related research in academia, this dissertation introduces OpenRAM, a flexible, portable and open-source memory compiler and characterization methodology for generating and verifying memory designs across different technologies. Currently, this compiler generates GDSII-layout, SPICE netlists and timing/power characterization for single-port SRAMs using the FreePDK45 and SCMOS process design kits. 
 
In addition, SRAM designs, focusing on improving power consumption, access time and bitcell stability are explored in high variability advanced CMOS technologies. To have a stable read/write operation for SRAM in high variability process nodes, a differential-ended single-port 8T bitcell is proposed that improves the read noise margin, write noise margin and readout bitcell current by 45%, 48% and 21%, respectively, compared to a conventional 6T bitcell. Also, a differential-ended single-port 12T bitcell for subthreshold operation is proposed that solves the half-select disturbance and allows efficient bit-interleaving. 12T bitcell has a leakage control mechanism which helps to reduce the power consumption and provides operation down to 0.3 V. Both 8T and 12T bitcells are analyzed in a 64 kb SRAM array using 32 nm technology. Besides, to further improve the access time and power consumption, two tracking circuits (multi replica bitline delay and reconfigurable replica bitline delay techniques) are proposed to aid the generation of accurate and optimum sense amplifier set time. 
An error tolerant SRAM architecture suitable for low voltage video application with dynamic power-quality management is also proposed in this dissertation. This memory uses three power supplies to improve the SRAM stability in low voltages. The proposed triple-supply approach achieves 63% improvement in image quality and 69% reduction in power consumption compared to a single-supply 64 kb SRAM array at 0.70 V.